What are the pixel encodings of HDMI?

The HDMI protocol supports a resolution of 640×480p at 59.94Hz. The pixel encoding formats that the HDMI protocol can support include RGB4:4:4, YCbCr4:4:4, and YCbCr4:2:2. The source end can adaptively select the optimal pixel encoding format based on the EDID information and its own functions.

Most of the source-end and receiver-end devices support pixels with a color depth of 24-bit. Some source-end and receiver-end devices can support pixels with color depths of 24-bit, 30-bit, 36-bit, and 48-bit. When the color depth exceeds 24-bit, it is called the "dark color" mode. Each dark color mode mainly supports RGB4:4:4, and a few can choose to support YCbCr 4:4:4. Not all dark color modes need to support YCbCr 4:2:2. The pixel encoding formats and color depths indicated by EDID should be supported by the receiver-end under normal circumstances, but in actual transmission, due to various reasons (such as hardware failures, compatibility issues, etc.), the receiver-end may be unable to process certain formats or depths normally, and although the source-end will adapt according to the EDID information, it cannot completely guarantee that it will not send pixel encoding formats and color depths that the receiver-end does not support. 
HDMI can send three different pixel encoding formats: RGB4:4:4, YCbCr 4:4:4, and YCbCr 4:2:2. It supports four color depths. Different versions of HDMI standards have different support situations for different pixel encoding formats at different color depths. Usually, RGB4:4:4 and YCbCr4:4:4 allow depths greater than 24-bit. As shown in the figure, when the color depth of RGB4:4:4 is 24-bit, the transmission mode is as follows: the R, G, and B components of the first pixel are transmitted in the first pixel of the video transmission cycle.

The 24-bit YCbCr 4:2:2 transmission method: The high 8 bits of the Y component are transmitted on channel 1, and the low 4 bits are on channel 0. The high 8 bits of the C component are on channel 2, and the low 4 bits are on channel 0. Since the data of the YCbCr 4:2:2 format requires only two components for each pixel, more bits are allocated to each component. The available 24 bits are divided into a 12-bit Y component and a 12-bit C component. The first pixel period transmits Y0 and CB0, and the second pixel period transmits Y1 and CR0.

HDMI supports three color depths, namely 24 bit/pixel, 36 bit/pixel and 48 bit/pixel. Usually, RGB4:4:4 and YCbCr4:4:4 allow a depth greater than 24 bits, which is the "dark" mode. Taking 24 bit/pixel as an example, the rate at which the TMDS clock carries pixel data is one pixel per clock. When the color depth is greater than 24 bit/pixel, due to the need to transmit additional bits, the TMDS clock runs faster than the sampling clock. The ratio of the TMDS clock rate to the sampling clock rate is consistent with the ratio of the color depth to 24-bit.

The audio data and auxiliary data are transmitted in the form of data packets during the data island cycle, while the HSYNC (horizontal synchronization signal) and VSYNC (vertical synchronization signal) signals are mainly represented implicitly or explicitly through specific control characters during the control cycle. During the video data transmission cycle, the HSYNC and VSYNC signals exist and are used to synchronize the scanning of the video's lines and fields. Although they are not transmitted as independent physical signals as in traditional analog video, in the encoding and control mechanism of HDMI, synchronization information is conveyed through control characters and other means, and the receiving end will use this information to display the video correctly. When transmitting control information, multiple combinations of control characters are used in the control cycle to convey various control information including the synchronization signals, and the encoding and usage of these control characters follow a complex mechanism specified by the HDMI protocol. All receiving ends that comply with the HDMI standard contain an EDID data structure that can be accessed through the DDC channel. The source end obtains the EDID information by the signal source and converts it to the required format to provide the correct format to the receiving end. Generally, the transmission rate of the source end should not exceed the maximum TMDS clock rate supported by the receiving end. In the DDC channel, the data is synchronized with the serial clock (Serial Clock, SCL) signal in the I2C bus, so it should follow the I2C standard mode, which means the maximum clock rate is 100 kHz. The source end reads the EDID information from the receiving end using I2C commands.